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MD1810
Initial Release
High Speed Quad MOSFET Driver
Features
6ns rise and fall time with 1000pF load 2A peak output source/sink current 1.2V to 5V input CMOS compatible 5V to 12V total supply voltage Smart Logic threshold Low jitter design Four matched channels Outputs can swing below ground Output is high impedence when disabled Low inductance package High-performance thermally-enhanced
General Description
The Supertex MD1810 is a high-speed quad MOSFET driver. It is designed to drive high voltage P-and N-channel MOSFETs for medical ultrasound imaging applications. The MD1810 can also be used for ultrasound metal flaw detection, nondestructive evaluation test, piezoelectric transducer drive, clock drive, and PIN diode drive. The MD1810 has four inputs which individually control four outputs. It also has an output enable (OE) pin. When OE is low, all of the outputs will be in a high impedance state regardless of their logic input control. When OE is high, the MD1810 sets the threshold logic transition to (VOE+VGND)/2. This ensures the transition to always be at half the amplitude of the logic input signal. This allows the device to have inherent propagation delay matching regardless of the logic input amplitude. The output stage of the MD1810 has separate power connections enabling the output signal L and H levels to be chosen independently from the VDD and VSS supply voltages. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and -5 volts, and the output L and H levels may be varied anywhere over the range of -5 to +5 volts. The output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance present.
Applications
Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver CCD Clock driver/buffer High speed level translator
Typical Application Circuit
+100V +12V +12V 1.0F 0.47F 0.47F VDD OE INA OUTA VH 10nF
10nF
-100V 1.0F +10V
3.3V CMOS Logic Inputs
INB
OUTB
Supertex TC6320TG
INC
OUTC
1.0F
IND
OUTD
10nF
GND VSS VL 10nF Supertex MD1810 Supertex TC6320TG 1.0F -10V
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Ordering Information
DEVICE MD1810 JA Package Option 16-Lead 4x4x0.9 QFN MD1810K6-G 45C/W (1oz. 4-layer 3x4inch PCB) Product Marking Information 1
ST
MD1810
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings*
VDD-VSS, Logic Supply Voltage VH, Output High Supply Voltage VL, Output Low Supply Voltage Vss, Low Side Supply Voltage Logic Input Levels Maximum Junction Temperature Storage Temperature Soldering Temperature Package Power Dissipation -0.5V to +13.5V VL-0.5V to VDD+0.5V VSS-0.5V to VH+0.5V -7V to +0.5V VSS-0.5V to VSS+7V +125C -65C to 150C 235C 2.2W
Line
Device Number Year, Week Code, Lot Number
1810 YWLL
2ND Line
Example: 5A88 means Lot #88 of first or second week in 2005
Pin 1
1810 YWLL
Top View
*Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
DC Electrical Characteristics (V
Sym.
VDD-VSS VSS VH VL IDDQ IHQ IDD IH VIH VIL IIH IIL VIH VIL RIN CIN
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Logic supply voltage Low side supply voltage Output high supply voltage Output low supply voltage VDD quiescent current VH quiescent current VDD average current VH average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance
H
Min.
4.5 -5.5 VSS+2 VSS
Typ.
Max.
13 0 VDD VDD-2
Units
V V V V mA A mA mA
Conditions
0.8 10 7.0 18 VOE-0.3 0 5 0.3 1.0 1.0 1.2 0 12 20 5 5 0.3 30 10
No input transitions, OE = 1 One channel on at 5.0Mhz, No load
V V A A V V K pF For logic input OE For logic inputs INA, INB, INC, and IND
Outputs (V
Sym.
RSINK RSOURCE ISINK ISOURCE
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Output sink resistance Output source resistance Peak output sink current Peak output source current
Min.
Typ.
Max.
12.5 12.5
Units
A A
Conditions
ISINK = 50mA ISOURCE = 50mA
2.0 2.0
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AC Electrical Characteristics (V
Sym.
tirf tPLH tPHL tPOE tr tf l tr - tf l l tPLH-tPHL l tdm
MD1810
H
= VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C)
Parameter
Input or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to output Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay matching
Min.
Typ.
Max.
10
Units
ns ns ns ns ns ns ns
Conditions
Logic input edge speed requirement
7 7 9 6 6 1.0 1.0 2.0
CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns
for each channel ns ns Device to device delay match
Logic Truth Table
Logic Inputs OE
H H L
IN
L H X
Output
VL VH High Z
Timing Diagram and VTH / VOE Curve
VTH vs VOE
VTH
1.8V IN 0V tPLH 12V OUT 0V
10% 90 % 50% 5 0%
VOE/2
2.0 1.5
tPHL
9 0%
1.0 0.6V 0.5
10%
0
tr
tf
0
1.0
2.0
3.0
4.0
5.0
VOE
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Simplified Block Diagram
MD1810
Detailed Block Diagram
OE Level Shifter
VDD
VH
VSS VDD
OUTA
INA
Level Shifter VSS VDD VL VH
VSS VDD
OUTB
INB
Level Shifter VSS VDD VL VH
VSS VDD
OUTC
INC
Level Shifter VSS VDD VL VH
VSS VDD
OUTD
IND
Level Shifter
SUB
GND
VSS
VL
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Typical Applications
2-Channel +100V to -100V Pulser
+100V
MD1810
+12V
+12V
0.1F
0.47F 0.47F VDD OE INA OUTA VH
10nF To Piezoelectric Transducer
10nF
-100V
INB 3.3V CMOS Logic Inputs INC
OUTB
Supertex TC6320TG
0.1F +100V
OUTC
0.1F
IND
OUTD
10nF To Piezoelectric Transducer
GND VSS VL
10nF
Supertex MD1810
Supertex TC6320TG
-100V
0.1F
Single Channel 100V to 0V Pulser
+12V
+12V 0.47F 0.47F VDD VH
10nF
+100 V 0.1F
To Piezoelectric Transducer
OE INA OUTA
10nF
-100V
INB 3.3V CMOS Logic Inputs INC
OUTB
Supertex TC6320
0.1F
OUTC
IND
OUTD
GND VSS VL
Supertex MD1810
Supertex TC2320
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MD1810
Application Information
For proper operation of the MD1810, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND to VLL, where VLL is 1.2 to 5.0 volts. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1810 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS, and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry.
Pin Description
VDD VSS VH VL GND OE INA, INB,INC, IND OUTA, OUTB, OUTC, OUTD Substrate High side supply voltage. Low side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies and powered-up first. Supply voltage for P-channel output stage. Supply voltage for N-channel output stage. Logic input ground reference. Output enable logic input. When OE is high, (VOE+VGND)/2 sets the threshold transition between logic level high and low. When OE is low, all outputs are at high impedance. Keep OE low until IC powered up. Logic input. Input logic high will cause the output to swing to VH. Input logic low will cause the output to swing to VL. Keep all logic inputs low until IC powered up. Output drivers The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally.
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MD1810
Pin Configuration
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Note
Function INB VL GND VL INC IND VSS OUTD OUTC VH VH OUTB OUTA VDD INA OE
Thermal Pad, and Pin #7 (VSS), must be connected externally
2.64 16 13
1
12
QFN-16 4x4x0.9
4 9
2.64
5 0.325 0.65
8 0.28
(Top View, mm)
Doc.# DSFP - MD1810
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